Click here to see my CV. And here to see my Google Scholar

 

• Journals
• Conferences
• National Conferences
• My Ph.D. Thesis
• Physics Journals & Conferences
• Patents
• Technical Reports
  

   

1. "Efficient Inter-core Power and Thermal Balancing for Multicore Processors"
   Juan M. Cebrián, Daniel Sánchez, Juan L. Aragón and Stefanos Kaxiras
   Computing, [DOI: 10.1007/s00607-012-0236-6], November 2012
   
   
2. "A Fault-Tolerant Architecture for Parallel Applications in Tiled-CMPs"  (pdf) 
   Daniel Sánchez, Juan L. Aragón and José M. García
   The Journal of Supercomputing, vol. 61, no. 3, pp. 997-1023, September 2012
   
   
3. "Leakage-efficient Design of Value Predictors through State and Non-state Preserving Techniques"  (pdf)
   Juan M. Cebrián, Juan L. Aragón, José M. García and Stefanos Kaxiras
   The Journal of Supercomputing, vol. 55, no. 1, pp. 28-50, January 2011
   
   
4. "Exploiting Address Compression and Heterogeneous Interconnects for Efficient Message Management in Tiled CMPs"   (pdf)
   Antonio Flores, Manuel E. Acacio and Juan L. Aragón
   Journal of Systems Architecture,  vol. 56, no. 9, pp. 429-441, September 2010
   
   
5. "Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs"  (pdf)
   Antonio Flores, Juan L. Aragón and Manuel E. Acacio
   IEEE Transactions on Computers, vol. 59, no. 1, pp. 16-28, January 2010
   
   
6. "Optimizing CAM-Based Instruction Cache Designs for Low-Power Embedded Systems"  (pdf)
   Juan L. Aragón and Alex Veidenbaum
   Journal of Systems Architecture, vol. 54, no. 12, pp. 1155-1163, December 2008
   
   
7. "An Energy Consumption Characterization of On-Chip Interconnection Networks for Tiled CMP Architectures"  (pdf)
   Antonio Flores, Juan L. Aragón and Manuel E. Acacio
   The Journal of Supercomputing, vol. 45, no. 3, pp. 341-364, September 2008
   
   
8. "Control Speculation for Energy-Efficient Next-Generation Superscalar Processors"  (pdf)
   Juan L. Aragón, José González and Antonio González
   IEEE Transactions on Computers, vol. 55, no. 3, pp. 281-291, March 2006
   
   
9. "Managing Power Constraints in a Single-core Scenario through Power Tokens"
   Juan M. Cebrián, Juan L. Aragón and Stefanos Kaxiras
   Submitted for review
   
   
10. "Soft-Error Mitigation by means of Decoupled Transactional Memory Threads"
    Daniel Sánchez, José M. García and Juan L. Aragón
    Submitted for review
    
    
11. "Modelling the impact of permanent faults in caches"
    Daniel Sánchez, Yiannakis Sazeides, Juan M. Cebrián, José M. García and Juan L. Aragón
    Ongoing a major review in IEEE Transactions on Computers
    
    

   

12. "Token3D: Reducing Temperature in 3D die-stacked CMPs through Cycle-level Power Control Mechanisms"
    Juan M. Cebrián, Juan L. Aragón and Stefanos Kaxiras
    In Proc. of the 17th Int. Conference on Parallel and Distributed Computing (Euro-Par), Bordeaux, France, August 2011
    
    
13. "An Analytical Model for the Calculation of the Expected Miss Ratio in Faulty Caches"
    Daniel Sánchez, Yiannakis Sazeides, Juan L. Aragón and José M. García
    In Proc. of the 17th IEEE International On-Line Testing Symposium (IOLTS), Athens, Greece, July 2011
    
    
14. "Power Token Balancing: Adapting CMPs to Power Constraints for Parallel Multithreaded Workloads"
    Juan M. Cebrián, Juan L. Aragón and Stefanos Kaxiras
    In Proc. of the 25th IEEE Int. Parallel & Distributed Processing Symposium (IPDPS), Anchorage, Alaska, USA, May 2011
    
    
15. "A Log-Based Redundant Architecture for Reliable Parallel Computation"
    Daniel Sánchez, Juan L. Aragón and José M. García
    In Proc. of the 17th Int. Conference on High Performance Computing (HiPC), Goa, India, December 2010
    
    
16. "MLP-aware Instruction Queue Resizing: The Key to Power-Efficient Performance"
    Pavlos Petoumenos, G. Psychou, Stefanos Kaxiras, Juan M. Cebrián and Juan L. Aragón
    Lecture Notes in Computer Science, vol. 5974, pp. 113-125, February 2010
    In Proc. of the 23rd Int. Conference on Architecture of Computing Systems (ARCS), Hannover, Germany, February 2010
    
    
17. "Energy-Efficient Hardware Prefetching for CMPs using Heterogeneous Interconnects"
    Antonio Flores, Juan L. Aragón and Manuel E. Acacio
    In Proc. of the 18th Euromicro International Conference on Parallel, Distributed and Network-Based Computing (EUROMICRO-PDP), Pisa, Italy, February 2010
    
    
18. "FATSEA – An Architectural Simulator for General Purpose Computing on GPUs"
    Kenneth E. Østby, Juan L. Aragón, José M. García and Manuel Ujaldón
    In Proc. of the 2nd Workshop on Rapid Simulation & Performance Evaluation: Methods and Tools (RAPIDO), in conjunction with HiPEAC’10, Pisa, Italy, January 2010
    
    
19. "REPAS: Reliable Execution for Parallel Applications in Tiled-CMPs"
    Daniel Sánchez, Juan L. Aragón and José M. García
    Lecture Notes in Computer Science, vol. 5704, pp. 321-333, August 2009
    In Proc. of the 15th Int. Conference on Parallel and Distributed Computing (Euro-Par), Delft, Netherlands, August 2009
    
    
20. "Efficient Microarchitecture Policies for Accurately Adapting to Power Constraints"
    Juan M. Cebrián, Juan L. Aragón, José M. García, Pavlos Petoumenos and Stefanos Kaxiras
    In Proc. of the 23rd IEEE Int. Parallel & Distributed Processing Symposium (IPDPS), Rome, Italy, May 2009
    
    
21. "Extending SRT for Parallel Applications in Tiled-CMP Architectures"
    Daniel Sánchez, Juan L. Aragón and José M. García
    In Proc. of the 14th IEEE Workshop on Dependable Parallel, Distributed and Network-Centric Systems (DPDNS), in conjunction with IPDPS'09, Rome, Italy, May 2009
    
    
22. "Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs"
    Antonio Flores, Manuel E. Acacio and Juan L. Aragón
    In Proc. of the 37th IEEE Int. Conference on Parallel Processing (ICPP), Portland, OR, USA, September 2008
    
    
23. "Evaluating Dynamic Core Coupling in a Scalable Tiled-CMP Architecture"
    Daniel Sánchez, Juan L. Aragón and José M. García
    In Proc. of the 7th Int. Workshop on Duplicating, Deconstructing, and Debunking (WDDD), in conjunction with ISCA'08, Beijing, China, June 2008
    
    
24. "Efficient Message Management in Tiled CMP Architectures using a Heterogeneous Interconnection Network"
    Antonio Flores, Juan L. Aragón and Manuel E. Acacio
    Lecture Notes in Computer Science, vol. 4873, pp. 133-146, December 2007
    In Proc. of the 14th Int. Conference on High Performance Computing (HiPC), Goa, India, December 2007
    
    
25. "Adaptive VP Decay: Making Value Predictors Leakage-efficient Designs for High Performance Processors"
    Juan M. Cebrián, Juan L. Aragón, José M. García and Stefanos Kaxiras
    In Proc. of the 4th ACM Int. Conference on Computing Frontiers (CF), Ischia, Italy, May 2007
    
    
26. "Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures"
    Antonio Flores, Juan L. Aragón and Manuel E. Acacio
    In Proc. of the 4th IEEE Int. Symp. on Embedded Computing (SEC), Niagara Falls, Canada, May 2007
    
    
27. "Leakage Energy Reduction in Value Predictors through Static Decay"
    Juan M. Cebrián, Juan L. Aragón and José M. García
    In Proc. of the 3rd Int. Workshop on High-Performance, Power-Aware Computing (HP-PAC), in conjunction with IPDPS'07, Long Beach, CA, USA, March 2007
    
    
28. "Energy-Effective Instruction Fetch Unit for Wide Issue Processors"
    Juan L. Aragón and Alex Veidenbaum
    Lecture Notes in Computer Science, Springer-Verlag, vol. 3740, pp. 15-27, October 2005
    In Proc. of the 10th Asia-Pacific Computer Systems Architecture Conference (ACSAC), Singapore, October 2005
    
    
29. "Energy–Efficient Design for Highly Associative Instruction Caches in Next–Generation Embedded Processors"
    Juan L. Aragón, Dan Nicolaescu, Alex Veidenbaum and Ana-Maria Badulescu
    In Proc. of the International Conference on Design, Automation and Test in Europe (DATE), Paris, France, February 2004
    
    
30. "Power-Aware Control Speculation through Selective Throttling"
    Juan L. Aragón, José González and Antonio González
    In Proc. of the 9th IEEE International Symposium on High Performance Computer Architecture (HPCA), Anaheim, CA, USA, February 2003
    
    
31. "Dual Path Instruction Processing"
    Juan L. Aragón, José González, Antonio González and James E. Smith
    In Proc. of the 16th ACM International Conference on Supercomputing (ICS), New York, NY, USA, June 2002
    
    
32. "Confidence Estimation for Branch Prediction Reversal"
    Juan L. Aragón, José González, José M. García and Antonio González
    Lecture Notes in Computer Science, Springer-Verlag, vol. 2228, pp. 214-223, December 2001
    In Proc. of the 8th International Conference on High Performance Computing (HiPC), Hyderabad, India, December 2001
    
    
33. "Selective Branch Prediction Reversal by Correlating with Data Values and Control Flow"
    Juan L. Aragón, José González, José M. García and Antonio González
    In Proc. of the 19th IEEE International Conference on Computer Design (ICCD), Austin, TX, USA, September 2001
    
    

   

34. "Reducing the Energy Consumption of Hardware Prefetching in Many-Core CMPs using Reply Partitioning"
    Antonio Flores, Manuel E. Acacio and Juan L. Aragón
    In Proc. of the XXII Jornadas de Paralelismo, La Laguna, Tenerife (Spain), September 2011
    
    
35. "Modelling Permanent Fault Impact on Cache Performance"
    Daniel Sánchez, Yiannakis Sazeides, Juan L. Aragón and José M. García
    In Proc. of the XXII Jornadas de Paralelismo, La Laguna, Tenerife (Spain), September 2011
    
    
36. "Mechanisms to Match Power Constraints in CMPs"
    Juan M. Cebrián, Juan L. Aragón and Stefanos Kaxiras
    In Proc. of the XXI Jornadas de Paralelismo, Valencia (Spain), September 2010
    
    
37. "Hardware Prefetching in Heterogeneous Interconnects: an Approach to Reducing Energy Consumption in Many-Core CMPs"
    Antonio Flores, Juan L. Aragón and Manuel E. Acacio
    In Proc. of the XXI Jornadas de Paralelismo, Valencia (Spain), September 2010
    
    
38. "Energy-Efficient Power Budget Matching"
    Juan M. Cebrián, Juan L. Aragón, José M. García, Pavlos Petoumenos and Stefanos Kaxiras
    In Proc. of the XX Jornadas de Paralelismo, A Coruña (Spain), September 2009
    
    
39. "Power-Aware On-Chip Network Management in Tiled CMPs using Address Compression"
    Antonio Flores, Manuel E. Acacio and Juan L. Aragón
    In Proc. of the XIX Jornadas de Paralelismo, Castellón (Spain), September 2008
    
    
40. "Adapting Dynamic Core Coupling to a Direct-Network Environment"
    Daniel Sánchez, Juan L. Aragón and José M. García
    In Proc. of the XIX Jornadas de Paralelismo, Castellón (Spain), September 2008
    
    
41. "An Adaptive Approach for Reducing Leakage Energy Consumption in Value Predictors"
    Juan M. Cebrián, Juan L. Aragón, José M. García and Stefanos Kaxiras
    In Proc. of the XVIII Jornadas de Paralelismo, Zaragoza (Spain), September 2007
    
    
42. "Reducing Leakage in Value Predictors by Using Decay Techniques"
    Juan M. Cebrián, Juan L. Aragón and José M. García
    In Proc. of the XVII Jornadas de Paralelismo, Albacete (Spain), September 2006
    
    
43. "Sim-PowerCMP: Un simulador de consumo para CMPs"
    Antonio Flores, Juan L. Aragón and Manuel E. Acacio
    In Proc. of the XVII Jornadas de Paralelismo, Albacete (Spain), September 2006
    
    
44. "Low-power Fetch Unit Design for Superscalar Processors"
    Juan L. Aragón and Alex Veidenbaum
    In Proc. of the XV Jornadas de Paralelismo, Almería (Spain), September 2004
    
    
45. "Branch Prediction Reversal by Correlating with Data Values"
    Juan L. Aragón, José González, José M. García and Antonio González
    In Proc. of the XII Jornadas de Paralelismo, Valencia (Spain), September 2001
    
    

   

• "Reducing Branch Misprediction Penalty through Confidence Estimation"
  Author: Juan L. Aragón
  Advisors: Pepe González (Intel Barcelona Research Center) and Antonio González (UPC and Intel Barcelona Research Center)
  University of Murcia (SPAIN) - February, 2003 (summa cum laude by unanimous decision)
  
  The goal of this Thesis is reducing the global penalty associated to branch mispredictions, in terms of both performance degradation and energy consumption, through the use of confidence estimation. The reduction of this global penalty has been achieved, firstly, by increasing the accuracy of branch predictors, next, by reducing the time necessary to restore the processor from a mispredicted branch, and finally, by reducing the energy consumption due to the execution of incorrect instructions.
  

   

46. "Dynamics of the eye’s wave aberration"
    H. Hofer, P. Artal, Juan L. Aragón and D.R. Williams
    In Journal of the Optical Society of America A, 18(3), pp. 497-506, March 2001
    
    
47. "Real-time double-pass system to study the dynamics of the eye's optical performance"
    Juan L. Aragón, N. López-Gil and P. Artal
    In Proc. of the EOS Topical Meeting on Physiological Optics, pp. 49-50, Wroclaw (Poland), Sep. 1999
    
    
48. "Dynamics of ocular aberrations during accommodation"
    P. Artal, H.J. Hofer, D.R. Williams and Juan L. Aragón
    In Proc. of the OSA Annual Meeting, California (USA), Sep. 1999
    
    
49. "Hartmann-Shack wavefront sensor in the eye: accuracy and performance limits"
    P. Artal, Juan L. Aragón, P.M. Prieto, F. Vargas-Martín and E. Berrio
    In Proc. of the Int. Workshop on Adaptive Optics for Industry and Medicine, pp. 39-44, Durham (England), July 1999
    
    
50. "Temporal characteristics of the eye's aberrations"
    H.J. Hofer, P. Artal, Juan L. Aragón and D.R. Williams
    In Journal of Inv. Ophth.Vis.Sci., 40(4), May 1999
    
    

   

• Title: "Rapid, Automatic measurement of the eye's wave aberration"
  Inventors: D.R. Williams, W.J. Vaughn, B.D. Singer, H. Hofer, G.Y. Yoon, P. Artal, Juan L. Aragón, P. Prieto and F. Vargas
  
  1. US Patent No.: 6,199,986 B1  (Mar. 13th, 2001)
  2. US Patent No.: 6,827,444 B2  (Dec. 7th, 2004)
  3. Singapore Patent No.: P-88309  (June 30th, 2005)
  4. Japan Patent No.: 4660047  (Jan. 7th, 2011)
     
     

   

• "Energy-Effective Instruction Fetch Unit for Very Wide Issue Processors"
  Juan L. Aragón and Alex Veidenbaum
  Technical Report #UM-DITEC-2004-1, University of Murcia, February 2004

• "Energy–Efficient Design for Highly Associative Instruction Caches in Next–Generation Embedded Processors"
  Juan L. Aragón, Dan Nicolaescu, Alex Veidenbaum and Ana-Maria Badulescu
  Technical Report #UM-DITEC-2003-1, University of Murcia, September 2003

• "Power-Aware Control Speculation through Selective Gating"
  Juan L. Aragón, José González and Antonio González
  Technical Report #UM-DITEC-2002-5, University of Murcia, March 2002

• "Dual Path Instruction Processing"
  Juan L. Aragón, José González, Antonio González and James E. Smith
  Technical Report #UM-DITEC-2001-9, University of Murcia, July 2001

• "Confidence Estimation Using Data Value Correlation for Branch Prediction Reversal"
  Juan L. Aragón, José González, José M. García and Antonio González
  Technical Report #UM-DITEC-2001-3, University of Murcia, February 2001

• "Selective Branch Prediction Reversal by Correlating on Data Values and Control Flow"
  Juan L. Aragón, José González, José M. García and Antonio González
  Technical Report #UM-DITEC-2000-8, University of Murcia, November 2000

        Last modified: Nov, 2012